FIG. 1 is a schematic functional block diagram illustrating a conventional phase locked loop (PLL). As shown in FIG. 1, the phase locked loop 10 includes a phase detector 101, a charge pump (CP) 103, a low pass filter (LF) 105 and a voltage control oscillator (VCO) 107. Moreover, the phase locked loop 10 is optionally equipped with a frequency divider 109. The operating principle of the phase locked loop 10 will be illustrated as follows. Firstly, a divided signal Vdiv from the frequency divider 109 and an input signal Vin are acquired. Then, a phase difference between the divided signal Vdiv and the input signal Vin is detected. According to the phase difference, the frequency fout of an output signal Vout from the voltage control oscillator 107 is adjusted. The frequency of the output signal Vout is divided by the frequency divider 109, and the divided signal Vdiv is issued to the phase detector 101. Ideally, the divided signal Vdiv is identical to the input signal Vin.
Please refer to FIG. 1 again. The output signal Vout from the voltage control oscillator 107 has a phase θout and a frequency fout. By the frequency divider 109, the frequency of the output signal Vout is divided, so that the divided signal Vdiv has a phase θdiv and a frequency fdiv. Moreover, the input signal Vin from the external source to the phase locked loop 10 has a phase θin.
The phase detector 101 will compare the phase θdiv of the divided signal Vdiv with the phase θin of the input signal Vin, thereby acquiring a phase difference (θin−θdiv). According to the phase difference, a set of phase comparing signal (Vup, Vdown) is issued from the phase detector 101 to the charge pump 103. The set of phase comparing signal (Vup, Vdown) is utilized by the charge pump 103 and the low pass filter 105 for outputting a control voltage. According to the control voltage, the output signal Von, from the voltage control oscillator 107 is adjusted.
FIG. 2A is a schematic circuit diagram illustrating a charge pump used in the conventional phase locked loop. As shown in FIG. 2A, the charge pump 103 includes a first current source unit 103a and a second current source unit 103b. The first current source unit 103a includes a first current source 1031 and a first switch 1033. The second current source unit 103b includes a second current source 1032 and a second switch 1034.
The first current source 1031 and the second current source 1032 of the charge pump 103 are employed to provide a first switching current IP and a second switching current IN, respectively. Depending on the on/off statuses of the switches 1033 and 1034, the low pass filter 105 is selectively charged or discharged by the first switching current IP and a second switching current IN through a control node Scont. Moreover, the first switch 1033 and the second switch 1034 are respectively turned on according to a first phase comparing signal Vup and a second phase comparing signal Vdown issued from the phase detector 101.
FIG. 2B is a waveform diagram illustrating the phase comparing signal outputted from the phase detector and the output current at the control node. The horizontal axis denotes time (t). The vertical axis denotes the voltage change of the phase comparing signals (Vup, Vdown) and the switching current outputted from the charge pump 103.
In a case that the first switch 1033 is turned on according to the first phase comparing signal Vup outputted from the phase detector 101, the charge pump 103 issues the first switching current IP. Under this circumstance, the low pass filter 105 is charged by the first switching current IP. That is, the duration of the high-level state of the first phase comparing signal Vup denotes the time period of outputting the first switching current IP. Moreover, the duration of the high-level state of the first phase comparing signal Vup also denotes the time period of charging the low pass filter 105 by the charge pump 103.
Whereas, in a case that the second switch 104 is turned on according to the second phase comparing signal Vdown outputted from the phase detector 101, the charge pump 103 issues the second switching current IN. According to the second switching current IN, the low pass filter 105 is discharged. That is, the duration of the high-level state of the second phase comparing signal Vdown denotes the time period of outputting the second switching current IN. Moreover, the duration of the high-level state of the second phase comparing signal Vdown also denotes the time period of discharging the low pass filter 105 by the charge pump 103.
From the above discussions, the low pass filter 105 is selectively charged or discharged by a combination of the first switching current IP and the second switching current IN, i.e. ICP. In the charge pump 103, the first current source unit 103a and the second current source unit 103b are implemented by p-channel metal-oxide-semiconductor (PMOS) transistors and n-channel metal-oxide-semiconductor (NMOS) transistors, respectively.
Ideally, the influences of the charging/discharging operations of the first current source unit 103a and the second current source unit 103b on the low pass filter 105 can be balanced. Since these two types of transistors are not completely symmetrical to each other, the magnitudes of the charging current and the discharging current are not completely equal to each other. That is, the magnitudes of the first switching current IP and the second switching current IN outputted from the control node Scont of the charge pump 103 are not identical.
Since the PMOS transistor and the NMOS transistor have different inherent characteristics, the first switching current IP generated by the PMOS transistor in the first current source unit 103a and the second switching current IN generated by the NMOS transistor in the second current source unit 103b are not always equal. Under this circumstance, the performance of the phase locked loop 10 is deteriorated. Therefore, there is a need of providing an improved charge pump to obviate the drawbacks encountered from the prior art.